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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Programmable Array Logic</span></span>

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</style><div role="note" class="hatnote navigation-not-searchable">Not to be confused with <a href="Programmable_logic_array" title="Programmable logic array">Programmable logic array</a>.</div>

<p><b>Programmable Array Logic</b> (<b>PAL</b>) is a family of <a href="Programmable_logic_device" title="Programmable logic device">programmable logic device</a> semiconductors used to implement <a href="Logic" title="Logic">logic</a> functions in digital <a href="Electrical_network" title="Electrical network">circuits</a> that was introduced by <a href="Monolithic_Memories" title="Monolithic Memories">Monolithic Memories</a>, Inc. (MMI) in March 1978.<sup id="cite_ref-MMI_PAL_Ad_1-0" class="reference"><a href="#cite_note-MMI_PAL_Ad-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> MMI obtained a registered trademark on the term PAL for use in "Programmable Semiconductor Logic Circuits". The trademark is currently held by <a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice Semiconductor</a>.<sup id="cite_ref-PAL_trademark_2-0" class="reference"><a href="#cite_note-PAL_trademark-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup>

</p><p>PAL devices consisted of a small <a href="Programmable_read-only_memory" class="mw-redirect" title="Programmable read-only memory">PROM</a> (programmable read-only memory) core and additional output logic used to implement particular desired logic functions with few components.

</p><p>Using specialized machines, PAL devices were "field-programmable". PALs were available in several variants:

</p>

<ul><li>"<a href="One-time_programmable" class="mw-redirect" title="One-time programmable">One-time programmable</a>" (OTP) devices could not be updated and reused after initial programming. (MMI also offered a similar family called HAL, or "hard array logic", which were like PAL devices except that they were mask-programmed at the factory.)</li>

<li>UV erasable versions (e.g.: PALCxxxxx e.g.: PALC22V10) had a quartz window over the chip die and could be erased for re-use with an ultraviolet light source just like an <a href="EPROM" title="EPROM">EPROM</a>.</li>

<li>Later versions (PALCExxx e.g.: PALCE22V10) were flash erasable devices.</li></ul>

<p>In most applications, electrically erasable <a href="Generic_array_logic" class="mw-redirect" title="Generic array logic">GALs</a> are now deployed as <a href="Pin-compatible" class="mw-redirect" title="Pin-compatible">pin-compatible</a> direct replacements for one-time programmable PALs.

</p>

<div class="mw-heading mw-heading2"><h2 id="History">History</h2></div>

<p>Before PALs were introduced, designers of digital logic circuits would use <a href="Small-scale_integration" class="mw-redirect" title="Small-scale integration">small-scale integration</a> (SSI) components, such as those in the <a href="7400_series" class="mw-redirect" title="7400 series">7400 series</a> TTL (<a href="Transistor-transistor_logic" class="mw-redirect" title="Transistor-transistor logic">transistor-transistor logic</a>) family; the 7400 family included a variety of logic building blocks, such as gates (<a href="NOT_gate" class="mw-redirect" title="NOT gate">NOT</a>, <a href="NAND_gate" title="NAND gate">NAND</a>, <a href="NOR_gate" title="NOR gate">NOR</a>, <a href="AND_gate" title="AND gate">AND</a>, <a href="OR_gate" title="OR gate">OR</a>), <a href="Multiplexers" class="mw-redirect" title="Multiplexers">multiplexers</a> (MUXes) and demultiplexers (DEMUXes), <a href="Flip-flop_(electronics)" title="Flip-flop (electronics)">flip-flops</a> (D-type, JK, etc.) and others. One PAL device would typically replace dozens of such "discrete" logic packages, so the SSI business declined as the PAL business took off. PALs were used advantageously in many products, such as <a href="Minicomputers" class="mw-redirect" title="Minicomputers">minicomputers</a>, as documented in <a href="Tracy_Kidder" title="Tracy Kidder">Tracy Kidder</a>'s best-selling book <i><a href="The_Soul_of_a_New_Machine" title="The Soul of a New Machine">The Soul of a New Machine</a></i>.

</p><p>PALs were not the first commercial programmable logic devices; <a href="Signetics" title="Signetics">Signetics</a> had been selling its <a href="Field_programmable_logic_array" class="mw-redirect" title="Field programmable logic array">field programmable logic array</a> (FPLA) since 1975. These devices were completely unfamiliar to most circuit designers and were perceived to be too difficult to use. The FPLA had a relatively slow maximum operating speed (due to having both programmable-AND and programmable-OR arrays), was expensive, and had a poor reputation for testability. Another factor limiting the acceptance of the FPLA was the large package, a 600-<a href="Thou_(unit_of_length)" class="mw-redirect" title="Thou (unit of length)">mil</a> (0.6", or 15.24 mm) wide 28-pin <a href="Dual_in-line_package" title="Dual in-line package">dual in-line package</a> (DIP).

</p><p>The project to create the PAL device was managed by <a href="John_Birkner" class="mw-redirect" title="John Birkner">John Birkner</a> and the actual PAL circuit was designed by H. T. Chua.<sup id="cite_ref-Birkner_1978_3-0" class="reference"><a href="#cite_note-Birkner_1978-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> In a previous job (at mini-computer manufacturer <a href="Computer_Automation" title="Computer Automation">Computer Automation</a>), Birkner had developed a 16-bit processor using 80 standard logic devices. His experience with standard logic led him to believe that user-programmable devices would be more attractive if the devices were designed to replace standard logic. This meant that the package sizes had to be more typical of the existing devices, and the speeds had to be improved. MMI intended PALs to be a relatively low cost (sub $3) part. However, the company initially had severe manufacturing yield problems and had to sell the devices for over $50. This threatened the viability of the PAL as a commercial product, and MMI was forced to license the product line to National Semiconductor. PALs were later "<a href="Second_source" title="Second source">second sourced</a>" by <a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a> and <a href="Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">Advanced Micro Devices</a>.

</p>

<div class="mw-heading mw-heading2"><h2 id="Process_technologies">Process technologies</h2></div>

<p>Early PALs were 20-pin <a href="Dual_in-line_package" title="Dual in-line package">DIP</a> components fabricated in silicon using bipolar transistor technology with one-time programmable (OTP) titanium-tungsten programming fuses.<sup id="cite_ref-TI_PAL_16R8_4-0" class="reference"><a href="#cite_note-TI_PAL_16R8-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> Later devices were manufactured by <a href="Cypress_Semiconductor" title="Cypress Semiconductor">Cypress</a>, <a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice Semiconductor</a> and <a href="Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">Advanced Micro Devices</a> using <a href="CMOS" title="CMOS">CMOS</a> technology.

</p><p>The original 20- and 24-pin PALs were denoted by MMI as <a href="Medium-scale_integration" class="mw-redirect" title="Medium-scale integration">medium-scale integration</a> (MSI) devices.

</p>

<div class="mw-heading mw-heading2"><h2 id="PAL_architecture">PAL architecture</h2></div>

<p>The PAL architecture consists of two main components: a logic plane and output logic macrocells.

</p>

<div class="mw-heading mw-heading3"><h3 id="Programmable_logic_plane">Programmable logic plane</h3></div>

<p>The programmable logic plane is a <a href="Programmable_read-only_memory" class="mw-redirect" title="Programmable read-only memory">programmable read-only memory</a> (PROM) array that allows the signals present on the device pins, or the logical complements of those signals, to be routed to output logic macrocells.

</p><p>PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-AND" plane used to implement "<a href="Disjunctive_normal_form" title="Disjunctive normal form">sum-of-products</a>" binary logic equations for each of the outputs in terms of the inputs and either synchronous or asynchronous feedback from the outputs.

</p>

<div class="mw-heading mw-heading3"><h3 id="Output_logic">Output logic</h3></div>

<p>The early 20-pin PALs had 10 inputs and 8 outputs. The outputs were active low and could be registered or combinational. Members of the PAL family were available with various output structures called "output logic macrocells" or OLMCs. Prior to the introduction of the "V" (for "variable") series, the types of OLMCs available in each PAL were fixed at the time of manufacture. (The PAL16L8 had 8 combinational outputs, and the PAL16R8 had 8 registered outputs. The PAL16R6 had 6 registered and 2 combinational outputs, while the PAL16R4 had 4 of each.) Each output could have up to 8 product terms (effectively AND gates); however, the combinational outputs used one of the terms to control a bidirectional output buffer. There were other combinations that had fewer outputs with more product terms per output and were available with active high outputs ("H" series).<sup id="cite_ref-mmi3_5-0" class="reference"><a href="#cite_note-mmi3-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 1–14">: 1–14 </span></sup> The "X" series of devices had an XOR gate before the register.<sup id="cite_ref-mmi3_5-1" class="reference"><a href="#cite_note-mmi3-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 1–9">: 1–9 </span></sup> There were also similar 24-pin versions of these PALs.

</p><p>This fixed output structure often frustrated designers attempting to optimize the utility of PAL devices because output structures of different types were often required by their applications. (For example, one could not get 5 registered outputs with 3 active high combinational outputs.) So, in June 1983 <a href="AMD" title="AMD">AMD</a> introduced the 22V10, a 24-pin device with 10 output logic macrocells.<sup id="cite_ref-22V10_Data_Sheet_6-0" class="reference"><a href="#cite_note-22V10_Data_Sheet-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> Each macrocell could be configured by the user to be combinational or registered, active high or active low. The number of product terms allocated to an output varied from 8 to 16. This one device could replace all of the 24-pin fixed function PAL devices. Members of the PAL "V" ("variable") series included the PAL16V8, PAL20V8 and PAL22V10.

</p>

<div class="gallerytext">PAL 16R4 block diagram</div>

</li>

<div class="gallerytext">AMD 22V10 block diagram</div>

</li>

<div class="gallerytext">AMD 22V10 output macrocell</div>

</li>

</ul>

<div class="mw-heading mw-heading2"><h2 id="Programming_PALs">Programming PALs</h2></div>

<p>PALs were programmed electrically using binary patterns (as <a href="JEDEC" title="JEDEC">JEDEC</a> <a href="ASCII" title="ASCII">ASCII</a>/<a href="Hexadecimal" title="Hexadecimal">hexadecimal</a> files) and a special electronic programming system available from either the manufacturer or a third party, such as <a href="Data_I/O_Corporation" class="mw-redirect" title="Data I/O Corporation">DATA I/O</a>. In addition to single-unit device programmers, device feeders and gang programmers were often used when more than just a few PALs needed to be programmed. (For large volumes, electrical programming costs could be eliminated by having the manufacturer fabricate a custom metal mask used to program the customers' patterns at the time of manufacture; MMI used the term "hard array logic" (HAL) to refer to devices programmed in this way.)

</p>

<div class="mw-heading mw-heading3"><h3 id="Programming_languages_(by_chronological_order_of_appearance)">Programming languages (by chronological order of appearance)</h3></div>

<p>Though some engineers programmed PAL devices by manually editing files containing the binary fuse pattern data, most opted to design their logic using a <a href="Hardware_description_language" title="Hardware description language">hardware description language</a> (HDL) such as Data I/O's <a href="Advanced_Boolean_Expression_Language" title="Advanced Boolean Expression Language">ABEL</a>, Logical Devices' CUPL, or MMI's <a href="PALASM" title="PALASM">PALASM</a>. These were <a href="Computer-assisted_design" class="mw-redirect" title="Computer-assisted design">computer-assisted design</a> (<a href="CAD" class="mw-redirect" title="CAD">CAD</a>) (now referred to as "<a href="Electronic_design_automation" title="Electronic design automation">electronic design automation</a>") programs which translated (or "compiled") the designers' logic equations into binary fuse map files used to program (and often test) each device.

</p>

<div class="mw-heading mw-heading4"><h4 id="PALASM">PALASM</h4></div>

<p>The <a href="PALASM" title="PALASM">PALASM</a> (from "PAL assembler") language was developed by <a href="John_Birkner" class="mw-redirect" title="John Birkner">John Birkner</a> in the early 1980s and the PALASM compiler was written by MMI in FORTRAN IV on an IBM 370/168. MMI made the source code available to users at no cost. By 1983, MMI customers ran versions on the <a href="Digital_Equipment_Corporation" title="Digital Equipment Corporation">DEC</a> <a href="PDP-11" title="PDP-11">PDP-11</a>, <a href="Data_General_NOVA" class="mw-redirect" title="Data General NOVA">Data General NOVA</a>, <a href="Hewlett-Packard" title="Hewlett-Packard">Hewlett-Packard</a> <a href="HP_2100" title="HP 2100">HP 2100</a>, MDS800 and others.

</p><p>It was used to express Boolean equations for the output pins in a text file, which was then converted to the 'fuse map' file for the programming system using a vendor-supplied program; later the option of translation from schematics became common, and later still, 'fuse maps' could be 'synthesized' from an <a href="Hardware_description_language" title="Hardware description language">HDL</a> (hardware description language) such as <a href="Verilog" title="Verilog">Verilog</a>.

</p>

<p>Assisted Technology released CUPL (<b>C</b>ompiler for <b>U</b>niversal <b>P</b>rogrammable <b>L</b>ogic) in September 1983.<sup id="cite_ref-Alford_1989_7-0" class="reference"><a href="#cite_note-Alford_1989-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> The software was always referred to as CUPL and never the expanded acronym. It was the first commercial design tool that supported multiple PLD families. The initial release was for the IBM PC and MS-DOS, but it was written in the <a href="C_programming_language" class="mw-redirect" title="C programming language">C programming language</a> so it could be ported to additional platforms.<sup id="cite_ref-CUPL_Datasheet_1983_8-0" class="reference"><a href="#cite_note-CUPL_Datasheet_1983-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> Assisted Technology was acquired by Personal CAD Systems (P-CAD) in July 1985. In 1986, PCAD's schematic capture package could be used as a front end for CUPL.<sup id="cite_ref-PCAD_1985_9-0" class="reference"><a href="#cite_note-PCAD_1985-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> CUPL was later acquired by Logical Devices and is now owned by <a href="Altium" title="Altium">Altium</a>.<sup id="cite_ref-CUPL_trademark_10-0" class="reference"><a href="#cite_note-CUPL_trademark-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> CUPL is currently available as an integrated development package for Microsoft Windows.<sup id="cite_ref-CUBEL_11-0" class="reference"><a href="#cite_note-CUBEL-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup>

</p><p><a href="Atmel" title="Atmel">Atmel</a> releases for free <a rel="nofollow" class="external text" href="http://www.atmel.com/tools/WINCUPL.aspx">WinCUPL</a> (their own design software for all Atmel SPLDs and CPLDs). Atmel was acquired by Microchip in 2016.

</p>

<p><a href="Data_I/O_Corporation" class="mw-redirect" title="Data I/O Corporation">Data I/O Corporation</a> released <a href="Advanced_Boolean_Expression_Language" title="Advanced Boolean Expression Language">ABEL</a> in April, 1984. The development team was Michael Holley, Mike Mraz, Gerrit Barrere, <a href="Walter_Bright" title="Walter Bright">Walter Bright</a>, Bjorn Freeman-Benson, Kyu Lee, David Pellerin, Mary Bailey, Daniel Burrier and Charles Olivier.

</p><p>Data I/O spun off the ABEL product line into an electronic design automation company called Synario Design Systems and then sold Synario to MINC Inc in 1997.

MINC was focused on developing FPGA development tools. The company closed its doors in 1998 and Xilinx acquired some of MINC's assets including the ABEL language and tool set. ABEL then became part of the Xilinx Webpack tool suite.

Now Xilinx owns ABEL.

</p>

<div class="mw-heading mw-heading3"><h3 id="Device_programmers">Device programmers</h3></div>

<p>Popular device programmers included <a href="Data_I/O_Corporation" class="mw-redirect" title="Data I/O Corporation">Data I/O Corporation</a>'s Model 60A Logic Programmer and Model 2900.

</p><p>One of the first PAL programmers was the Structured Design SD20/24. They had the PALASM software built-in and only required a CRT terminal to enter the equations and view the fuse plots. After fusing, the outputs of the PAL could be verified if test vectors were entered in the source file.

</p>

<div class="mw-heading mw-heading2"><h2 id="Successors">Successors</h2></div>

<p>After MMI succeeded with the 20-pin PAL parts introduced circa 1978, <a href="AMD" title="AMD">AMD</a> introduced the 24-pin 22V10 PAL with additional features. After buying out MMI (circa 1987), AMD spun off a consolidated operation as Vantis, and that business was acquired by <a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice Semiconductor</a> in 1999.<sup id="cite_ref-EE_Times_1999_12-0" class="reference"><a href="#cite_note-EE_Times_1999-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup>

</p><p>Altera introduced the EP300 (first CMOS PAL) in 1983 and later moved into the FPGA business.

</p><p>Lattice Semiconductor introduced the <a href="Generic_array_logic" class="mw-redirect" title="Generic array logic">generic array logic</a> (<a href="Generic_array_logic" class="mw-redirect" title="Generic array logic">GAL</a>) family in 1985, with functional equivalents of the "V" series PALs that used reprogrammable logic planes based on <a href="EEPROM" title="EEPROM">EEPROM</a> (electrically eraseable programmable read-only memory) technology. National Semiconductor was a <a href="Second_source" title="Second source">second source</a> for GAL parts.

</p>

<p>AMD introduced a similar family called PALCE. In general one GAL part is able to function as any of the similar family PAL devices. For example, the 16V8 GAL is able to replace the 16L8, 16H8, 16H6, 16H4, 16H2 and 16R8 PALs (and many others besides).

</p><p>ICT (International CMOS Technology) introduced the PEEL 18CV8 in 1986. The 20-pin CMOS EEPROM part could be used in place of any of the registered-output bipolar PALs and used much less power.

</p><p>Larger-scale programmable logic devices were introduced by <a href="Atmel" title="Atmel">Atmel</a>, <a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice Semiconductor</a>, and others. These devices extended the PAL architecture by including multiple logic planes and/or burying logic macrocells within the logic plane(s). The term <i><a href="Complex_programmable_logic_device" title="Complex programmable logic device">complex programmable logic device</a></i> (CPLD) was introduced to differentiate these devices from their PAL and GAL predecessors, which were then sometimes referred to as <i>simple programmable logic devices</i> (SPLDs).

</p><p>Another large programmable logic device is the <a href="Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate array</a> (FPGA). These are devices currently made by <a href="Intel" title="Intel">Intel</a> (who acquired <a href="Altera" title="Altera">Altera</a>) and <a href="Xilinx" title="Xilinx">Xilinx</a> (who was acquired by <a href="AMD" title="AMD">AMD</a>) and other semiconductor manufacturers.

</p>

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<ul><li><a href="Combinational_logic" title="Combinational logic">Combinational logic</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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</style><cite class="citation journal cs1">"Monolithic Memories announces: a revolution in logic design". <i>Electronic Design</i>. <b>26</b> (6). Rochelle, NJ: Hayden Publishing: 148B, 148C. March 18, 1978.</cite> Introductory advertisement on PAL (Programmable Array Logic).</span>

</li>

<li id="cite_note-PAL_trademark-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-PAL_trademark_2-0">^</a></b></span> <span class="reference-text">Monolithic Memories, Inc (MMI) filed for a work mark on the term "PAL" for use in "Programmable Semiconductor Logic Circuits" on April 13, 1978. A registered trademark was granted on April 29, 1980, registration number 1134025. MMI's first use of the term PAL in commerce was on February 21, 1978. The trademark is currently held by Lattice Semiconductor Corporation of Hillsboro, Oregon. Source: United States Patent and Trademark Office online database.</span>

</li>

<li id="cite_note-Birkner_1978-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-Birkner_1978_3-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFBirkner1978" class="citation journal cs1"><a href="John_Birkner" class="mw-redirect" title="John Birkner">Birkner, John</a> (August 16, 1978). "Reduce random-logic complexity". <i>Electronic Design</i>. <b>26</b> (17). Rochelle, NJ: Hayden Publishing: <span class="nowrap">98–</span>105.</cite></span>

</li>

<li id="cite_note-TI_PAL_16R8-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-TI_PAL_16R8_4-0">^</a></b></span> <span class="reference-text"><cite class="citation book cs1"><a rel="nofollow" class="external text" href="http://focus.ti.com/lit/ds/symlink/tibpal16r8-15c.pdf"><i>TIBPAL 16R8-15C Data Sheet</i></a> <span class="cs1-format">(PDF)</span>. Dallas TX: Texas Instruments. April 2000 [February 1984].</cite> "These IMPACT circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic." TI was a second source vendor for the MMI PALS.</span>

</li>

<li id="cite_note-mmi3-5"><span class="mw-cite-backlink">^ <a href="#cite_ref-mmi3_5-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-mmi3_5-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><cite id="CITEREFBirknerColi1983" class="citation book cs1">Birkner, John M.; Coli, Vincent J. (1983). <i>PAL Programmable Array Logic Handbook</i> (3rd ed.). Monolithic Memories, Inc.</cite></span>

</li>

<li id="cite_note-22V10_Data_Sheet-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-22V10_Data_Sheet_6-0">^</a></b></span> <span class="reference-text"><cite class="citation book cs1"><i>AmPAL 22V10 Advanced Information</i>. Sunnyvale CA: Advanced Micro Devices. June 1983. 04126A-PLP.</cite> Note: This is the data sheet published by AMD when the AmPAL 22V10 was introduced.</span>

</li>

<li id="cite_note-Alford_1989-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-Alford_1989_7-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFAlford1989" class="citation book cs1">Alford, Roger C. (1989). <i>Programmable Logic Designer's Guide</i>. Howard W. Sams. pp. <span class="nowrap">14–</span>15, <span class="nowrap">166–</span>168. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-672-22575-1</bdi>. <q>In 1981, [Bob] Osann started Assisted Technology to develop PLD support tools. In September 1983 Assisted Technology released version 1.01a of its CUPL (Universal Compiler for Programmable Logic) PLD compiler, supporting 29 devices.</q></cite></span>

</li>

<li id="cite_note-CUPL_Datasheet_1983-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-CUPL_Datasheet_1983_8-0">^</a></b></span> <span class="reference-text"><cite class="citation pressrelease cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131029195406/http://www.swtpc.com/mholley/PLD_History/ABEL_project/CUPL_Data_Sheet_1983_ocr.pdf">"CUPL - The Universal Language For Programmable Logic"</a> <span class="cs1-format">(PDF)</span> (Press release). San Jose, CA: Assisted Technology, Inc. 1983. Archived from <a rel="nofollow" class="external text" href="http://www.swtpc.com/mholley/PLD_History/ABEL_project/CUPL_Data_Sheet_1983_ocr.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2013-10-29<span class="reference-accessdate">. Retrieved <span class="nowrap">2013-08-10</span></span>.</cite> An early 1983 pre-release datasheet for CUPL.</span>

</li>

<li id="cite_note-PCAD_1985-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-PCAD_1985_9-0">^</a></b></span> <span class="reference-text"><cite class="citation journal cs1"><a rel="nofollow" class="external text" href="https://books.google.com/books?id=6mxHXqXKdFMC&pg=PA97">"Personal CAD Systems"</a>. <i>Computer World</i>. <b>19</b> (29). Framingham, MA: CW Communications: 97. July 22, 1985. <a href="ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0010-4841">0010-4841</a>.</cite></span>

</li>

<li id="cite_note-CUPL_trademark-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-CUPL_trademark_10-0">^</a></b></span> <span class="reference-text">US Patent and Trademark Office. "CUPL" Computer software, namely, software used to develop and compile designs for programmable logic devices, and related user manuals distributed therewith. First used in 1983, status Active. Serial Number 76357007. Registration Number 2909461. Owner: Altium Limited, Australia 3 Minna Close, Belrose NSW2085, Australia.</span>

</li>

<li id="cite_note-CUBEL-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-CUBEL_11-0">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150529134635/http://www.logicaldevices.com:80/cubel.htm">"CUBEL ChipDesigner 5.0"</a>. Logical Devices. August 2013. Archived from <a rel="nofollow" class="external text" href="http://www.logicaldevices.com/cubel.htm">the original</a> on May 29, 2015.</cite></span>

</li>

<li id="cite_note-EE_Times_1999-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-EE_Times_1999_12-0">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.eetimes.com/document.asp?doc_id=1213080">"Lattice Semiconductor Acquires Vantis Corp. from AMD"</a>. <i>EE Times</i>. 26 April 1999<span class="reference-accessdate">. Retrieved <span class="nowrap">May 13,</span> 2015</span>.</cite></span>

</li>

</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2></div>

<dl><dt>Books</dt></dl>

<ul><li><i>Programmable Logic Designer's Guide</i>; Roger Alford; <a href="Sams_Publishing" title="Sams Publishing">Sams Publishing</a>; 1989; <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-672-22575-1</bdi>. <small><a rel="nofollow" class="external text" href="https://archive.org/details/programmablelogi0000alfo/">(archive)</a></small></li>

<li><i>PAL Programmable Logic Handbook</i>; 4ed; <a href="Monolithic_Memories" title="Monolithic Memories">Monolithic Memories</a>; 1985. <small><a rel="nofollow" class="external text" href="https://archive.org/details/MonolithicMemories-MMI-ProgrammableLogicHandbookOCR/">(archive)</a></small></li></ul>

<dl><dt>Databooks</dt></dl>

<ul><li><i>Bipolar LSI 1984 Databook</i>; 5ed; <a href="Monolithic_Memories" title="Monolithic Memories">Monolithic Memories</a>; 1984. <small><a rel="nofollow" class="external text" href="https://archive.org/details/bipolar-lsi-1984-databook-fifth-edition/">(archive)</a></small></li></ul>

<dl><dt>Specifications</dt></dl>

<ul><li><i>Standard Data Transfer Format Between Data Preparation System and Programmable Logic Device Programmer</i>; JEDEC Standard JESD3-C; <a href="JEDEC" title="JEDEC">JEDEC</a>; June 1994.</li></ul>

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</style><div id="Programmable_logic116" style="font-size:114%;margin:0 4em"><a href="Programmable_logic_device" title="Programmable logic device">Programmable logic</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Concepts</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Logic_block" title="Logic block">Logic block</a></li></ul></li>

<li><a href="Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a>

<ul><li><a href="Xputer" title="Xputer">Xputer</a></li></ul></li>

<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li>

<li><a href="Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li>

<li><a href="High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li>

<li><a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Verilog" title="Verilog">Verilog</a>

<li><a href="VHDL-VITAL" class="mw-redirect" title="VHDL-VITAL">VITAL</a></li></ul></li>

<li><a href="SystemVerilog" title="SystemVerilog">SystemVerilog</a>

<li><a href="SystemC" title="SystemC">SystemC</a></li>

<li><a href="Handel-C" title="Handel-C">Handel-C</a></li>

<li><a href="PALASM" title="PALASM">PALASM</a></li>

<li><a href="MyHDL" title="MyHDL">MyHDL</a></li>

<li><a href="Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Accellera" title="Accellera">Accellera</a></li>

<li><a href="Achronix" title="Achronix">Achronix</a></li>

<li><a href="Aldec" title="Aldec">Aldec</a></li>

<li><a href="Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li>

<li><a href="Infineon_Technologies" title="Infineon Technologies">Infineon</a></li>

<li><a href="Intel" title="Intel">Intel</a></li>

<li><a href="Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li>

<li><a href="Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li>

<li><a href="Siemens" title="Siemens">Siemens</a></li>

<li><a href="Synopsys" title="Synopsys">Synopsys</a></li>

<li><a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Stratix" title="Stratix">Stratix</a></li>

<li><a href="Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Intel_Quartus_Prime" class="mw-redirect" title="Intel Quartus Prime">Intel Quartus Prime</a></li>

<li><a href="Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li>

<li><a href="Vivado" title="Vivado">Vivado</a></li>

<li><a href="ModelSim" title="ModelSim">ModelSim</a></li>

<li><a href="List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Intellectual_property" title="Intellectual property">Intellectual<br>property</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M</a></li>

<li><a href="LatticeMico8" title="LatticeMico8">LatticeMico8</a></li>

<li><a href="MicroBlaze" title="MicroBlaze">MicroBlaze</a></li>

<li><a href="PicoBlaze" title="PicoBlaze">PicoBlaze</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="LatticeMico32" title="LatticeMico32">LatticeMico32</a></li>

<li><a href="OpenCores" title="OpenCores">OpenCores</a></li>

<li><a href="OpenRISC" title="OpenRISC">OpenRISC</a>

<li><a href="Power_ISA" title="Power ISA">Power ISA</a>

<ul><li><a href="Libre-SOC" title="Libre-SOC">Libre-SOC</a></li>

<li><a href="OpenPOWER_Microwatt" title="OpenPOWER Microwatt">Microwatt</a></li></ul></li>

</div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Digital_electronics118" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Digital_electronics118" style="font-size:114%;margin:0 4em"><a href="Digital_electronics" title="Digital electronics">Digital electronics</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Electronic_component" title="Electronic component">Components</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Transistor" title="Transistor">Transistor</a></li>

<li><a href="Resistor" title="Resistor">Resistor</a></li>

<li><a href="Inductor" title="Inductor">Inductor</a></li>

<li><a href="Capacitor" title="Capacitor">Capacitor</a></li>

<li><a href="Printed_electronics" title="Printed electronics">Printed electronics</a></li>

<li><a href="Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li>

<li><a href="Electronic_circuit" title="Electronic circuit">Electronic circuit</a></li>

<li><a href="Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li>

<li><a href="Combinational_logic" title="Combinational logic">Combinational logic</a></li>

<li><a href="Sequential_logic" title="Sequential logic">Sequential logic</a></li>

<li><a href="Logic_gate" title="Logic gate">Logic gate</a></li>

<li><a href="Boolean_circuit" title="Boolean circuit">Boolean circuit</a></li>

<li><a href="Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li>

<li><a href="Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a> (HIC)</li>

<li><a href="Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li>

<li><a href="Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">Three-dimensional integrated circuit</a> (3D IC)</li>

<li><a href="Emitter-coupled_logic" title="Emitter-coupled logic">Emitter-coupled logic</a> (ECL)</li>

<li><a href="Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">Erasable programmable logic device</a> (EPLD)</li>

<li><a href="Macrocell_array" title="Macrocell array">Macrocell array</a></li>

<li><a href="Programmable_logic_array" title="Programmable logic array">Programmable logic array</a> (PLA)</li>

<li><a href="Programmable_logic_device" title="Programmable logic device">Programmable logic device</a> (PLD)</li>

<li><a href="Generic_Array_Logic" title="Generic Array Logic">Generic Array Logic</a> (GAL)</li>

<li><a href="Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li>

<li><a href="Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li>

<li><a href="Field-programmable_object_array" title="Field-programmable object array">Field-programmable object array</a> (FPOA)</li>

<li><a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a> (ASIC)</li>

<li><a href="Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Theory</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Digital_signal" title="Digital signal">Digital signal</a></li>

<li><a href="Boolean_algebra" title="Boolean algebra">Boolean algebra</a></li>

<li><a href="Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li>

<li><a href="Logic_in_computer_science" title="Logic in computer science">Logic in computer science</a></li>

<li><a href="Computer_architecture" title="Computer architecture">Computer architecture</a></li>

<li><a href="Digital_signal_(signal_processing)" title="Digital signal (signal processing)">Digital signal</a>

<ul><li><a href="Digital_signal_processing" title="Digital signal processing">Digital signal processing</a></li></ul></li>

<li><a href="Circuit_minimization_for_Boolean_functions" class="mw-redirect" title="Circuit minimization for Boolean functions">Circuit minimization</a></li>

<li><a href="Switching_circuit_theory" title="Switching circuit theory">Switching circuit theory</a></li>

<li><a href="Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Electronics_design" class="mw-redirect" title="Electronics design">Design</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li>

<li><a href="Place_and_route" title="Place and route">Place and route</a>

<ul><li><a href="Placement_(electronic_design_automation)" title="Placement (electronic design automation)">Placement</a></li>

<li><a href="Routing_(electronic_design_automation)" title="Routing (electronic design automation)">Routing</a></li></ul></li>

<li><a href="Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a></li>

<li><a href="Register-transfer_level" title="Register-transfer level">Register-transfer level</a>

<ul><li><a href="Hardware_description_language" title="Hardware description language">Hardware description language</a></li>

<li><a href="High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li></ul></li>

<li><a href="Formal_equivalence_checking" title="Formal equivalence checking">Formal equivalence checking</a></li>

<li><a href="Synchronous_circuit" title="Synchronous circuit">Synchronous logic</a></li>

<li><a href="Asynchronous_circuit" title="Asynchronous circuit">Asynchronous logic</a></li>

<li><a href="Finite-state_machine" title="Finite-state machine">Finite-state machine</a>

<ul><li><a href="Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical state machine</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Computer_hardware" title="Computer hardware">Computer hardware</a>

<ul><li><a href="Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul></li>

<li><a href="Digital_audio" title="Digital audio">Digital audio</a>

<ul><li><a href="Digital_radio" title="Digital radio">radio</a></li></ul></li>

<li><a href="Digital_photography" title="Digital photography">Digital photography</a></li>

<li><a href="Telephony#Digital_telephony" title="Telephony">Digital telephone</a></li>

<li><a href="Digital_video" title="Digital video">Digital video</a>

<ul><li><a href="Digital_cinematography" title="Digital cinematography">cinematography</a></li>

<li><a href="Digital_television" title="Digital television">television</a></li></ul></li>

<li><a href="Electronic_literature" title="Electronic literature">Electronic literature</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Design issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Metastability_(electronics)" title="Metastability (electronics)">Metastability</a></li>

<li><a href="Runt_pulse" title="Runt pulse">Runt pulse</a></li></ul>

</div></td></tr></tbody></table></div>

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This article is issued from <a class="external text" title="Last edited on 2025-07-14" href="https://en.wikipedia.org/wiki/?title=Programmable_Array_Logic&oldid=1300484426">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

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